STOIC: state assignment based on output/input functions

Author

Pomeranz, Irith ; Cheng, Kwang-Ting

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

Volume

12

Issue

8

fYear

1993

fDate

8/1/1993 12:00:00 AM

Firstpage

1123

Lastpage

1131

Abstract

A finite-state-machine (FSM) synthesis procedure, specifically aimed at using primary inputs and primary output functions as state variables, is proposed. The number of next-state functions that have to be implemented is thus reduced, potentially reducing the area of the synthesized circuit. Also, as more of the state variables are directly observable (the primary outputs used as state variables), and directly controllable (the primary inputs used as state variables) the testability of the implementation is increased. Experimental results are given to demonstrate the effectiveness of the procedure in reducing area

Keywords

design for testability; finite state machines; logic CAD; state assignment; FSM synthesis procedure; STOIC; finite-state-machine; next-state functions; output/input functions; state variables; testability; Circuit synthesis; Circuit testing; Cities and towns; Combinational circuits; Delay; Encoding; Helium; Minimization; Sequential circuits; State estimation;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.238605

Filename

238605