Bifurcation analysis for third-order phase-locked loops

Second-order phase-locked loops (PLLs) are extensively used in applications related to recovering clock signals for synchronous demodulation in telecommunication networks. In situations where an improvement of the transient response of the local clocks is necessary, third-order PLLs are employed. Here, we use concepts taken from dynamical system theory for analytically determining the capture range of three nonlinear third-order PLLs subject to a ramp input. We show that saddle-node, saddle-saddle, and Hopf bifurcations can be produced by varying the values of the input signal velocity and of the PLL parameters, providing criteria for designing such PLLs.