Interconnect-based system-level energy and power prediction to guide architecture exploration

We present a novel technique to predict energy and power consumption in an electronic system, given its behavioral specification and library components. The early prediction gives circuit designers the freedom to make numerous high-level choices (such as die size, package type, and latency of the pipeline) with confidence that the final implementation will meet power and energy as well as cost and performance constraints. Our unique statistical estimation technique associates low-level, technology dependent physical and electrical parameters, with expected circuit resources and interconnect. Further correlations with switching activity yield accurate results consistent with implementations. All feasible designs are investigated using this technique and the designer may tradeoff between small size, high speed, low energy, and low power. The results for designs of two popular signal processing applications, predicted prior to synthesis, are within 10% accuracy of power estimates performed on synthesized layouts.