Title :
Circuit Structure and Switching Function Verification
Author :
Du, Min-Wen ; Weiss, C.Dennis
fDate :
6/1/1973 12:00:00 AM
Abstract :
A new approach is presented for the design of multiple fault detection tests in which the structure of a combinational circuit is used to reduce the number of input combinations required. The structure is defined by the interconnection of the basic elements, each of arbitrary complexity. The fault model assumes that the functions realized by the basic elements may undergo any deviation whatsoever, but that the circuit structure is fault free. Thus, arbitrary combinations of multiple faults within one or more basic elements are included in the model. Decomposition theory can be used to verify that a set of input combinations is a multiple fault detection test set under this model. A process called expansion will be introduced to simplify this task. A well-defined procedure is given for deriving a suitable test set which for some circuits is minimal or near minimal. It will yield a multiple fault detection test of length less than 2n for any circuit with a nontrivial nondisjoint decomposition, defined by a basic-element partition. Higher order basic-element partitions are introduced as a generalization. An upper bound is given on the length of a multiple fault detection test for any circuit with a given structure, independent of the function realized on the structure. The bound is tighter when function information is also used.
Keywords :
Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Computer science; Electrical fault detection; Fault detection; Integrated circuit interconnections; Switching circuits; Upper bound; Combinational logic networks; fault detection; functional decomposition; multiple faults;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1973.5009116