Title :
Derivation of Minimal Test Sets for Monotonic Logic Circuits
Author :
Dandapani, Ramaswami
Author_Institution :
Department of Computer Science, The University of Iowa, Iowa City, Iowa 52240.
fDate :
7/1/1973 12:00:00 AM
Abstract :
It is shown that the number of maximal false vertices and minimal true vertices is the minimum number of tests required to detect all s-a-1 and s-a-0 faults in any irredundant two-level realization of a 2-monotonic function.
Keywords :
Circuit faults; Circuit testing; Digital circuits; Electrical fault detection; Fault detection; Input variables; Inverters; Logic circuits; Logic testing; Fault detection; minimal test set; monotonic functions; multiple fault detection; threshold functions; unate functions;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1973.5009131
