• DocumentCode
    960190
  • Title

    Derivation of Minimal Test Sets for Monotonic Logic Circuits

  • Author

    Dandapani, Ramaswami

  • Author_Institution
    Department of Computer Science, The University of Iowa, Iowa City, Iowa 52240.
  • Issue
    7
  • fYear
    1973
  • fDate
    7/1/1973 12:00:00 AM
  • Firstpage
    657
  • Lastpage
    661
  • Abstract
    It is shown that the number of maximal false vertices and minimal true vertices is the minimum number of tests required to detect all s-a-1 and s-a-0 faults in any irredundant two-level realization of a 2-monotonic function.
  • Keywords
    Circuit faults; Circuit testing; Digital circuits; Electrical fault detection; Fault detection; Input variables; Inverters; Logic circuits; Logic testing; Fault detection; minimal test set; monotonic functions; multiple fault detection; threshold functions; unate functions;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.1973.5009131
  • Filename
    5009131
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=960190