Title :
High-speed binary multiplier
Author_Institution :
University of Cambridge, Engineering Department, Cambridge, UK
Abstract :
A multiplier is described which uses a `tree¿ of adders to add the partial products, resulting in a considerable increase in speed when the adders have a carry-propagation delay per bit which is appreciably less than the addition delay.
Keywords :
adders; delays; multiplying circuits; adders; delay; high speed binary multiplier; tree;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19710190
