Title :
Universal Test Sets for Logic Networks
Author :
Akers, Sheldon B., Jr.
Author_Institution :
Electronics Laboratory, General Electric Company, Syracuse, N.Y. 13201.
Abstract :
This paper examines the problem of finding a single universal test set that will test any of a variety of different implementations of a given switching function. It is shown that, for AND/OR networks, universal test sets may be found that detect not only all single faults but all multiple faults as well. The minimality and size of these sets are examined and their derivation for incomplete functions is described.
Keywords :
Automata; Circuit faults; Circuit testing; Electronic equipment testing; Fault detection; Fault diagnosis; Helium; Logic testing; Microelectronics; Next generation networking; Fault detection; functional testing; multiple faults; single faults; stuck-at-faults; universal test sets;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1973.5009174
