Module frequency estimation and noise budget limitations/trade-offs in multichip modules as a function of CMOS chips integration

A detailed investigation of the estimation of module clock frequency and of the limitations due to system noise containment as a function of CMOS chip integration level of multichip assemblies is performed. The objective is to analyze the overall noise limitations, and to predict the system performance as a function of integration level. Results demonstrate that unwanted coupled noise and simultaneous switching noise are a major degradation/limitation factor with high levels of integration in multichip modules (MCMs). This effect is especially a major limiting factor with scaled and reduced-supply-voltage CMOS chips. Closed-form equations for estimating the module frequency and the overall noise budget for MCMs are given. Design curves are shown for CMOS MCM system frequency, and noise budget limitations are discussed for various levels of chip integration. Results from case studies on performance and noise limits of future workstation MCMs are explained