• DocumentCode
    961026
  • Title

    LSI Packaging that Passes PIND Test

  • Author

    Porto, Joseph F Dal ; Loescher, Douglas H. ; Olson, Harry C. ; Plunkett, Paul V.

  • Author_Institution
    Sandia National Lab., NM
  • Volume
    4
  • Issue
    4
  • fYear
    1981
  • fDate
    12/1/1981 12:00:00 AM
  • Firstpage
    471
  • Lastpage
    475
  • Abstract
    A packaged large-scale integrated (LSI) chip or hybrid destined for military or space applications must pass the gambit of screens listed in Method 5004 of MIL-STD-883B. These screens include the particle impact noise detection (PIND) test in which a sensitive acoustic transducer listens for loose particles inside a package while the package is vibrated and shocked. Prior to instituting new assembly procedures, PIND test yields were as low as 20 percent. We have used scanning electron microscopy (SEM) and energy dispersive analysis X-rays (EDAX) [1] to identify the particles that caused PIND test failures and have developed and are now using assembly procedures that result in a low reject rate at PIND testing. With these procedures, 3099 packages have been PIND tested with 155 failures noted, resulting in yields that exceed 94 percent. The assemblies consisted of a 1 K random access memory (RAM) die with dimensions of 3.5 x 6.1 x 0.031 mm thick which is attached with gold/silicon eutectic to a 24-pin leadless hermetic package. Packages were solder sealed in a belt furnace with a gold-tin eutectic alloy preform and a nickel and gold plated Kovar lid. The major particle type which caused PIND test failures was determined to be gold-tin spheres from the gold-tin preform. To a much lesser degree, other particles such as calcium silicate, gold, and silicone were noted. The effect of furnace temperature, furnace ambient, and package orientation on the number of gold-tin solder balls detected in the sealed packages was investigated. The best results were obtained if the sealing furnace ambient was nonoxidizing, peak temperature was approximately 360°C, and the packages were sealed in a 45° lid down position.
  • Keywords
    Integrated circuit packaging; Integrated circuit testing; Acoustic noise; Acoustic testing; Assembly; Furnaces; Gold; Large scale integration; Packaging; Preforms; Scanning electron microscopy; Temperature;
  • fLanguage
    English
  • Journal_Title
    Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0148-6411
  • Type

    jour

  • DOI
    10.1109/TCHMT.1981.1135818
  • Filename
    1135818