Bipolar Charge Trapping Induced Anomalous Negative Bias-Temperature Instability in HfSiON Gate Dielectric pMOSFETs

Negative bias-temperature (NBT) stress-induced drain current instability in a pMOSFET with a gate stack is investigated by using a fast transient measurement technique. We find that in certain stress conditions, the NBT-induced current instability evolves from enhancement mode to degradation mode, giving rise to an anomalous turn-around characteristic with stress time and stress gate voltage. Persistent poststress drain current degradation is found in a pMOSFET, as opposed to drain current recovery in its n-type MOSFET counterpart. A bipolar charge trapping model along with trap generation in a HfSiON gate dielectric is proposed to account for the observed phenomena. Poststress single charge emissions from trap states in HfSiON are characterized. Charge pumping and carrier separation measurements are performed to support our model. The impact of NBT stress voltage, temperature, and time on drain current instability mode is evaluated.