DocumentCode :
961181
Title :
Global optimization approach for architectural synthesis
Author :
Gebotys, Catherine H. ; Elmasry, Mohamed I.
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada
Volume :
12
Issue :
9
fYear :
1993
fDate :
9/1/1993 12:00:00 AM
Firstpage :
1266
Lastpage :
1278
Abstract :
A relaxed linear programming model which simultaneously schedules and allocates functional units and registers is presented for synthesizing cost-constrained globally optimal architectures. This approach is important for industrial applications, because it provides exploration of optimal synthesized architectures and early architectural decisions have the greatest impact on the final design. An integer programming formulation of the architectural synthesis problem is transformed into the mode packing problem. Polyhedral theory is used to formulate constraints that decrease the size of the search space, thus improving solution efficiency. Execution times are an order of magnitude faster than for previous heuristic techniques. The present approach breaks new ground by (1) simultaneously scheduling and allocating in practical execution times, (2) guaranteeing globally optimal solutions for a specific objective function, and (3) providing a polynomial run-time algorithm for solving some instances of this NP-complete problem
Keywords :
VLSI; circuit CAD; computational complexity; integer programming; linear programming; logic CAD; CAD; NP-complete problem; VLSI architecture; VLSI design; architectural synthesis; cost-constrained globally optimal architectures; globally optimal solutions; integer programming formulation; linear programming model; mode packing problem; optimal synthesized architectures; polynomial run-time algorithm; relaxed LP model; scheduling; Constraint theory; Cost function; Job shop scheduling; Linear programming; NP-complete problem; Polynomials; Runtime; Scheduling algorithm; Synthesizers; Upper bound;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.240074
Filename :
240074
Link To Document :
بازگشت