Title :
Fault simulation of parametric bridging faults in CMOS IC´s
Author :
Dalpasso, Marcello ; Favalli, Michele ; Olivo, Piero ; Riccò, Bruno
Author_Institution :
Dept. of Electron. & Comput. Sci., Bologna Univ., Italy
fDate :
9/1/1993 12:00:00 AM
Abstract :
The authors point out that the simulation of resistive bridging faults inside complex CMOS macrogates requires proper evaluation of resistances, in order to correctly determine realistic fault coverages. Here, an approach applicable to a large category of faults (bridgings, transistor stuck-ons, and node stuck-ats) that give rise to resistive paths between power supply and ground, and hence are all covered by the general term `bridging faults,´ is presented. This method, which avoids the single-fault-injection procedure, fault analysis is performed inside the macrogates aimed to determine the threshold resistance, thus discriminating whether or not a given fault is detectable as a logic error. This analysis is performed inside CMOS macro-gates whose output is observable. To fully characterize the quality of a test sequence with regard to resistive bridging faults, a new definition of fault coverage is presented, because the common concept of fault detection is not applicable to parametric faults
Keywords :
CMOS integrated circuits; circuit analysis computing; digital integrated circuits; fault location; integrated circuit testing; integrated logic circuits; logic testing; CMOS macrogates; digital ICs; fault analysis; fault coverages; fault detection; logic error; node stuck-ats; parametric bridging faults; resistive bridging faults; test sequence; threshold resistance; transistor stuck-ons; CMOS digital integrated circuits; CMOS integrated circuits; CMOS logic circuits; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit modeling; Integrated circuit testing; Performance analysis;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on