Acceleration of trace-based fault simulation of combinational circuits

The authors point out that significant improvements in the speed of fault simulation of combinational circuits have been achieved in recent years by combining parallel pattern simulation for the fault-free circuit with trace-based methods for identifying detected faults. Here, two concepts-joining stems for reducing explicit simulation of stem faults and quit lines for reducing backtracing within fanout-free regions-are presented. These concepts are used in a parallel-pattern trace-based simulation algorithm. Results of simulating the ISCAS85 benchmark combinational circuits with the proposed methods show their effectiveness both with and without fault-dropping