Title :
High-quality thin-film SOI technology using wafer bonding and selective polishing for VLSIs
Author :
Matsushita, Teruo ; Satoh, H. ; Hashimoto, Mime ; Ogasawara, A. ; Yamagishi, M. ; Yagi, A. ; Saitoh, Youichi ; Sakai, Shin´ichi
Author_Institution :
Sony Corp., Kanagawa, Japan
fDate :
11/1/1989 12:00:00 AM
Abstract :
Summary form only given. The authors have developed a novel technique for obtaining bulk quality thin-film SOI (silicon-on-insulator) by wafer bonding and selective polishing. 625- mu m-thick 5-in.-diameter
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; polishing; semiconductor technology; semiconductor-insulator boundaries; -0.8 V; 0.8 to 10 micron; 1 V; 30 nm; CMOS transistors; NMOS; PMOS; SURPASS; Si wafers; Si-SiO2; VLSI; gate lengths; mobility; oxide thickness; selective polishing; subthreshold slope; thin-film SOI technology; threshold voltage; two-dimensional process-device simulator; wafer bonding; Capacitance; Fabrication; MOS capacitors; Pulse measurements; Semiconductor films; Semiconductor thin films; Silicon on insulator technology; Substrates; Transistors; Very large scale integration; Wafer bonding;
Journal_Title :
Electron Devices, IEEE Transactions on
