A novel technique for fabrication of fully depleted CMOS devices in ultra-thin SOI films

Summary form only given. A novel technique which allows fabrication of CMOS devices in ultrathin silicon films without using the exotic source-drain metallization schemes has been developed. This technique, in the limit, will allow fabrication of devices in extremely thin (<50 nm) silicon films with relatively simple processing steps. The fabrication process starts with an SOI (silicon-on-insulator) substrate with a silicon film two to four times thicker than the final silicon thickness desired in the channel areas. LOCOS (local oxidation of silicon) with patterned Si₃N₄ oxidation mask followed by a wet oxide etch is used to thin the silicon film in the regions where transistor channels are to be located. This step also creates alignment marks for photolithography. Silicon film of the original higher thickness is retained in the nonchannel regions. Silicon mesas for n- and p-channel devices are formed next by aligning the mesa mask and plasma etching the silicon film. The fabrication process beyond this point follows standard mesa-isolated SOI CMOS fabrication. Fully depleted n-channel devices with submicrometer effective channel lengths were fabricated in SIMOX (separation by implantation of oxygen) substrates of original silicon thicknesses of 200 nm and characterized to illustrate the new technique.