Title :
An Architecture for Bitonic Sorting with Optimal VLSI Performnance
Author :
Bilardi, Gianfranco ; Preparata, Franco P.
Author_Institution :
Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL.
fDate :
7/1/1984 12:00:00 AM
Abstract :
We propose a class of designs of a new interconnection network, the pleated cube-connected cycles (PCCC), which can impleement stable bitonic sorting of n records of size q in area A = O(q2n2/T2), where T, the computation time, is in the range [¿(q log2 n), O(q ¿n/(q+ log n))]. Thus, this network is an AT2,/R-optimal bitonic sorter in the synchronous VLSI model of computation under the word-local restriction.
Keywords :
Computational modeling; Computer networks; Concurrent computing; Intelligent networks; Semiconductor device measurement; Size measurement; Sorting; Stability; Upper bound; Very large scale integration; Area-time tradeoff; VLSI complexity; bitonic sorting; cubeconnected cycles; optimal algorithms; parallel computation;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1984.5009338
