Title :
VLSI Sorting with Reduced Hardware
Author :
Ja´Ja´, Joseph ; Owens, Robert Michael
Author_Institution :
Department of Computer Science, Pennsylvania State University, University Park, PA 16802.; Department of Electrical Engineering, University of Maryland, College Park, MD 20742.
fDate :
7/1/1984 12:00:00 AM
Abstract :
We propose a new VLSI architecture which allows many problems to be solved quite efficiently on chips with very small processing areas. We consider in detail the sorting problem and show how it can be solved quickly and elegantly on our model. We show that sorting n numbers can be done on a chip with processing area A = o(n) with an almost optimal speedup in a network with mesh-connected interconnections. The control is shown to be simple and easily implementable in VLSI.
Keywords :
Computer architecture; Discrete Fourier transforms; Flip-flops; Fourier transforms; Hardware; Random access memory; Read-write memory; Shift registers; Sorting; Very large scale integration; Architecture; VLSI; hardware; sorting;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1984.5009340
