• DocumentCode
    962275
  • Title

    Design of reprogrammable FPLA

  • Author

    Rajsuman, R.

  • Author_Institution
    Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
  • Volume
    25
  • Issue
    11
  • fYear
    1989
  • fDate
    5/25/1989 12:00:00 AM
  • Firstpage
    715
  • Lastpage
    716
  • Abstract
    A new design scheme for field programmable logic arrays is presented. The proposed design uses transistors with double polysilicon gates instead of fuses. The design is highly useful since the PLA can be programmed again and again without any constraint. The proposed design offers the concept of reusable hardware to implement combinational circuits.
  • Keywords
    MOS integrated circuits; PLD programming; combinatorial circuits; integrated logic circuits; logic arrays; logic design; NMOS technology; combinational circuits; design scheme; double polysilicon gates; field programmable logic arrays; reprogrammable FPLA; reusable hardware; transistors;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19890484
  • Filename
    24096
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=962275