Title :
A New PLA Design for Universal Testability
Author_Institution :
Department of Electronic Engineering, Osaka University, Osaka 565, Japan.
Abstract :
A new design of universally testable PLA´s is presented in which all multiple faults can be detected by a universal test set which is independent of the function being realized by the PLA. The proposed design has the following properties. 1) It can be tested with function-independent test patterns; hence, no test pattern generation is required. 2) The amount of extra hardware is significantly decreased compared to the previous designs of universally testable PLA´s. 3) Very high fault coverage is achieved, i. e., all single and multiple stuck faults, crosspoint faults, and adjacent line bridging faults are detected. 4) It is appropriate for built-in testing approaches. 5) It can be applied to the high-density PLA´s using array folding techniques.
Keywords :
Circuit faults; Circuit testing; Cyclic redundancy check; Fault tolerance; Logic arrays; Logic design; Logic testing; Notice of Violation; Programmable logic arrays; Shift registers; Built test; PLA folding; design for testability; fault detection; function-independent test; programmable logic array (PLA); testing; universal test;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1984.5009363
