DocumentCode :
962711
Title :
Analysis of Read Current and Write Trip Voltage Variability From a 1-MB SRAM Test Structure
Author :
Fischer, Thomas ; Amirante, Ettore ; Huber, Peter ; Nirschl, Thomas ; Olbrich, Alexander ; Ostermayr, Martin ; Schmitt-Landsiedel, Doris
Author_Institution :
Inst. of Tech. Electron., Tech. Univ. Munchen, Munich
Volume :
21
Issue :
4
fYear :
2008
Firstpage :
534
Lastpage :
541
Abstract :
We present an area efficient test structure that allows measurement of the statistical distribution of SRAM cell read currents and write trip voltages for 1 million SRAM core cells. The data taken from measurements of wafers fabricated with a 90-nm and 65-nm CMOS process flow show that the device variations are Gaussian distributed for more than 1 million devices, covering more than 5 sigma of variation. The analysis of the measured SRAM performances validate Monte Carlo simulations.
Keywords :
CMOS memory circuits; Gaussian distribution; Monte Carlo methods; SRAM chips; semiconductor device testing; Gaussian distribution; Monte Carlo simulation; SRAM cell read currents; SRAM core cells; SRAM test structure; area efficient test structure; size 65 micron; size 90 nm; statistical distribution; write trip voltage variability; Area measurement; CMOS process; Current measurement; Fluid flow measurement; Performance analysis; Performance evaluation; Random access memory; Statistical distributions; Testing; Voltage; 65 and 90 nm; SRAM; low voltage; measurement structure; read current; variation; write trip voltage;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2008.2004329
Filename :
4657436
Link To Document :
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