Low Temperature Double-Exposed Polyimide/Oxide Dielectric for VLSI Multilevel Metal Interconnection

By use of a double-exposed (double-etch) low temperature polyimide/oxide process, the packing density for both first and second level metal interconnection can be improved by some 35 percent and 30 percent, respectively, in the vicinity Of the via. Moreover, the complete interconnect process may be realized at temperatures below 300°C. Since polyimide can be applied in thick layers having negligible (tensile) stress, a planar surface results and also parasitic lead capacitances may be considerably reduced. This process is also amenable to either wet chemical or dry plasma processing.