A Hypergraph Model for Fault-Tolerant VLSI Processor Arrays

We study here a formal version of a strategy for constructing fault-tolerant VLSI processor arrays in an environment of wafer-scale integration. The strategy achieves tolerance to faults by running buses past the implemented PE´s and interconnecting the fault-free ones into an array of the desired structure by having PE´s tap into the bank of buses. Earlier studies [12] have shown this strategy to be competitive with more familiar strategies, particularly given the availability of laser-welding technology. We study here fault-tolerant implementation of linear arrays and tree-structured arrays, deriving both upper and lower bounds on the area required to lay out the fault-tolerant arrays. We also consider briefly the issue of wire lengths.