Properties of Wired Logic

Author

Kambayashi, Yahiko ; Muroga, Saburo

Author_Institution

Department of Computer Science, University of Illinois, Urbana, IL 61801.; Department of Computer Science and Communication Engineering, Kyushu University, Fukuoka, 812, Japan.

Issue

6

fYear

1986

fDate

6/1/1986 12:00:00 AM

Firstpage

550

Lastpage

563

Abstract

When we design networks with NOR or NAND gates which are implemented with bipolar and MOS transistors, wired logic is usually allowed. The usage of wired logic reduces the network cost and possibly improves the speed because of shorter delays on wired logic than on a gate. Typical logic functions performed by wired logic are AND and OR, which are called wired-AND and wired-OR, respectively. Properties of networks with NOR gates and wired-AND (or wired-OR) are discussed. Some of these properties are used in developing synthesis procedures of optimum networks by the integer programming logic design method. For all three-variable functions, the optimum networks with NOR gates and wired-OR´s, designed by this synthesis approach, are shown.

Keywords

Computer science; Costs; Joining processes; Logic circuits; Logic design; Logic functions; Logic gates; Logic programming; MOSFETs; Network synthesis; Integer programming; NOR gate; logic design; optimum network; wired logic; wired-AND; wired-OR;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.1986.5009432

Filename

5009432