Design of a Hih-Speed Square Root Multiply and Divide Unit

Author

Zurawski, J.H.P. ; Gosling, J.B.

Author_Institution

Department of Computer Science, University of Manchester, M13 9PL, England.; Digital Equipment Corporation, Littleton, MA 01460.

Issue

1

fYear

1987

Firstpage

13

Lastpage

23

Abstract

In this paper radix-4 algorithms for square root and division are developed. The division algorithm evaluates the more useful function xz/y. These algorithms are shown to be suitable for implementing as a unified hardware unit which evaluates square root, division, and multiplication. Cost reductions in the hardware are obtained by use of gate arrays. A design based on the Motorola MCA2500 series of Macrocell gate array (MCA) is presented. At a cost of 9 MCA´s and 16 commercial ECL 100 K parts a 64-bit square root can be evaluated in 750 us using worst case delays. Division takes 710 ns and multiplication 325 ns. Redundancy in the digit set together with carry-save adders are used to achieve this high performance.

Keywords

Algorithm design and analysis; Arithmetic; Computer aided instruction; Costs; Delay; Frequency; Hardware; Intersymbol interference; Logic; Uninterruptible power systems; Computer arithmetic; division; gate array implementation; multiplication; redundant number systems; square root algorithm;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/TC.1987.5009445

Filename

5009445