Title :
Time Redundant Fault-Location in Bit-Sliced ALU´s
Author_Institution :
Department of Electrical Engineering and Technology, and the Computer Center, National Taiwan Institute of Technology, Taipei, Taiwan 10772, Republic of China.
Abstract :
A method of fault location in arithmetic and logic units (ALU´s) is proposed. When the failures are confined to adjacent bit slices of the ALU´s, the RESO (recomputing with shifted operands) based method can isolate the faulty bit slices by specifying a larger set of ``suspicious´´ faulty bit slices, and, therefore, identify the definitely fault-free bit slices in ALU´s. The method is applicable to both arithmetic and logic operations.
Keywords :
Arithmetic; Error correction; Fault detection; Fault diagnosis; Fault location; Fault tolerance; Logic; Process design; Redundancy; Reliability theory; ALU; RESO; bit slice; error detection; faulty location; time redundancy;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1987.5009483
