Title :
On Error Indication for Totally Self-Checking Systems
Author :
Nanya, Takashi ; Kawamura, Toshiaki
Author_Institution :
Department of Computer Science, Tokyo Institute of Technology, Tokyo 152, Japan.
Abstract :
Different ways of defining a totally self-checking system are discussed. Based on the discussion, a self-testing error indicator is defined and shown to provide a useful means to ensure concurrent error detection for fault-tolerant systems. A simple design for the self-testing error indicator is presented.
Keywords :
Adders; Built-in self-test; Circuit faults; Combinational circuits; Concurrent computing; Fault detection; Fault location; Fault tolerant systems; Logic design; Redundancy; Checker; code-disjoint; concurrent error detection; error indicators; fault secure; self-testing; totally self-checking systems;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1987.5009484
