Abstract :
The design and development of the million-transistor N10 chip, which is aimed at workstations and supercomputers, is described. This superfast microprocessor is also the company´s first chip to use a reduced instruction set. The chip is designed for testability, executes each instruction in one clock cycle, and features on-chip parallelism.<>
Keywords :
microprocessor chips; reduced instruction set computing; Intel; N10 chip; on-chip parallelism; reduced instruction set; supercomputers; superfast microprocessor; testability; workstations; CMOS technology; Computer architecture; Computer graphics; Design engineering; Electric shock; Microcomputers; Microprocessors; Reduced instruction set computing; Supercomputers; Workstations;
