Race-free state assignments for synthesizing large-scale asynchronous sequential logic circuits

A state assignment technique is introduced for synthesizing large-scale asynchronous sequential logic circuits (ASLCs). It provides a systematic and efficient approach for generating race-free state assignments. A race condition is classified as being either an intrinsic race (IR) or or a generated race. Intrinsic races decompose into two subclassifications: visible intrinsic races and hidden intrinsic races. Algorithms have been developed to identify and eliminate these races. A graph, referred to as a Node-Weight Diagram, facilitates the process of making state assignments and guarantees that no races are generated. Moreover, it provides a convenient and efficient method for investigating the implications of selecting from an allowed set of alternative race-free state assignments. The state assignment technique described adds cycles and states, as needed, to avoid IRs and always attempts to use the minimum or near-minimum number of state variables and states. This technique has been implemented and incorporated into an ASLC design automation system. Experimental results show that it provides significantly better results than other approaches in terms of the computation time required to make the assignments and the number of state variables required to achieve race-free ASLCs