DocumentCode
964388
Title
Designing high-performance processors using real address prediction
Author
Hua, Kien A. ; Liu, Lishing ; Peir, Jih-Kwon
Author_Institution
Dept. of Comput. Sci., Central Florida Univ., Orlando, FL, USA
Volume
42
Issue
9
fYear
1993
fDate
9/1/1993 12:00:00 AM
Firstpage
1146
Lastpage
1151
Abstract
The authors propose design techniques that may significantly simplify the cache access path, and hence offer the opportunity of shorter cycle time or fewer pipeline stages. Their proposals are based on highly accurate prediction methods that allow them to efficiently resolve address translation information early in the pipe
Keywords
buffer storage; pipeline processing; address translation; cache access path; high-performance processors; pipeline stages; prediction methods; real address prediction; shorter cycle time; Application software; Central Processing Unit; Computer architecture; Galois fields; Hazards; Pipeline processing; Prediction methods; Process design; Proposals; Very large scale integration;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.241604
Filename
241604
Link To Document