Memory organization using imperfect bubble chips

A method is presented for using imperfect bubble chips having a major/minor loop scheme. The imperfect chips are allocated in a memory module in such a manner that defective minor loop groups are arranged in a predetermined regular relationship with respect to the positions of the defective groups within the chips. A statistical analysis is presented to determine the value of chip yield under the condition that existense of one or more defective groups within a chip are permissible. A memory system cost reduction of up to 50 percent is demonstrated for the fault-tolerant scheme chosen as an example, since the addition of the electronic circuit which enables the use of the imperfect chips is very simple.