Low-power and error protection coding for network-on-chip traffic

The power consumption of the network-on-chip communication backbone is explored and the effectiveness of low-power encoding and error protection techniques is analysed. For the switch under the study, a Nostrum deflective routing switch, simulations and power analysis suggest that only a minor fraction of the power is dissipated in the logic blocks, whereas the major part is due to the interconnection wires. The authors have investigated a number of low-power and data protection mechanisms and studied their impact on power consumption of the whole network. The bus-invert encoding scheme and a limited set of Hamming data protection codes have been implemented on both data link and at the network layer. However, it turned out that all low-power data encoding schemes have little potential to decrease power consumption due to the significant overhead. On the other hand, error protection mechanisms have a significant potential to decrease power consumption because they allow to operate the network at a lower voltage. The authors´ experiments show a 20% decrease of power consumption for a given error rate and for a given performance.