DocumentCode :
964960
Title :
Test Structure Methodology of IC Package Material Characterization
Author :
Edwards, Darvin R. ; Heinen, Gail ; Bednarz, George A. ; Schroen, Walter H.
Author_Institution :
Texas Instruments, Dallas, TX, USA
Volume :
6
Issue :
4
fYear :
1983
fDate :
12/1/1983 12:00:00 AM
Firstpage :
560
Lastpage :
567
Abstract :
A methodology in assembly/packaging technology of semiconductor integrated circuits (IC´s) is described Which serves a threefold purpose: it aims at characterizing and selecting electronic assembly/Packaging materials; it directs optimization and control of assembly/packaging processes; and it identifies failure mechanisms which determine product reliability. Case example applications of the methodology are reported including application to package molding compound characterization arid chip mount material selection. Conclusions are given in which a broadening of the methodology tO identify early warning indicators for prediction of later reliability failures is discussed.
Keywords :
Integrated circuit packaging; Integrated circuit testing; Assembly; Circuit testing; Electronics packaging; Integrated circuit packaging; Integrated circuit technology; Integrated circuit testing; Materials testing; Optimization methods; Semiconductor device packaging; Semiconductor materials;
fLanguage :
English
Journal_Title :
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
Publisher :
ieee
ISSN :
0148-6411
Type :
jour
DOI :
10.1109/TCHMT.1983.1136205
Filename :
1136205
Link To Document :
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