High-speed decoder of Reed-Solomon codes

Author

Wei, Shyue-Win ; Wei, Che-Ho

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsin Chu, Taiwan

Volume

41

Issue

11

fYear

1993

fDate

11/1/1993 12:00:00 AM

Firstpage

1588

Lastpage

1593

Abstract

A high speed decoding algorithm using a modified step-by-step method for t-error-correcting Reed-Solomon codes is introduced. Based on this algorithm, a sequential decoder and a vector decoder are then proposed. These two decoders can be constructed by four basic modules: the syndrome calculation module, the comparison module, the decision module, and the shift-control module. These decoders can be applied for both binary and nonbinary data transmissions working at high data rate. Because of the simplicity in structure and circuit realization, a decoder employing this algorithm can be easily implemented in a monolithic chip by the VLSI technology

Keywords

Reed-Solomon codes; VLSI; decoding; monolithic integrated circuits; Reed-Solomon codes; VLSI technology; binary data transmission; comparison module; decision module; error-correcting codes; high data rate; high speed decoding algorithm; monolithic chip; nonbinary data transmission; sequential decoder; shift-control module; syndrome calculation module; vector decoder; Binary codes; Circuits; Clocks; Code standards; Data communication; Error analysis; Helium; Iterative decoding; Reed-Solomon codes; Very large scale integration;

fLanguage

English

Journal_Title

Communications, IEEE Transactions on

Publisher

ieee

ISSN

0090-6778

Type

jour

DOI

10.1109/26.241736

Filename

241736