• DocumentCode
    965239
  • Title

    A digital phase-locked loop for generating frequency discriminating digital words

  • Author

    Saha, A.R. ; Mazumder, B.C.

  • Author_Institution
    Jadavpur University, Calcutta, India
  • Volume
    70
  • Issue
    2
  • fYear
    1982
  • Firstpage
    200
  • Lastpage
    201
  • Abstract
    The circuit configuration of the DPLL described in this paper is a modified version of the DPLL recently reported by the authors. Fast and symmetrical tracking has been achieved by the modified DPLL retaining the original properties of wide locking range and low frequency capability as an FM discriminator and frequency multiplier. Also, it is operable in a number of modes defined by their phases (0°, 180°, and 90°) and the frequency discriminating code X is scalable by the phase-lock logic design.
  • Keywords
    Availability; Counting circuits; Digital integrated circuits; Frequency conversion; Frequency locked loops; Logic circuits; Logic design; Logic gates; Output feedback; Phase locked loops;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/PROC.1982.12265
  • Filename
    1456533
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=965239