An architecture for WSI rapid prototyping

Author

Jain, Vijay K. ; Hikawa, Hiroomi ; Keezer, D.C.

Author_Institution

Center for Miocroelectron. Res., Univ. of South Florida, Tampa, FL, USA

Volume

25

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

71

Lastpage

75

Abstract

Wafer-scale integration architecture for rapid prototyping (WARP), a generalized architecture for rapid prototyping, is discussed. The primary goal of rapid prototyping is to map one of several members of a class of algorithms using a single-wafer architecture. The wafer can be personalized for the algorithm by either soft or hard-restructuring. The WARP wafer consists of an array of two types of cells specifically defined for this architecture: the universal multiply-subtract-add (UMSA) cell and the universal nonlinear (UNL) cell. Reconfiguration of the algorithms in the presence of defects, a harvesting probability model and yield, and wafer-scale testing and test facilities are described.<>

Keywords

VLSI; computer architecture; WARP; WSI; harvesting probability model; rapid prototyping; single-wafer architecture; universal multiply-subtract-add; wafer-scale testing; yield; Circuits; Computer architecture; Filtering algorithms; Finite impulse response filter; Matrix decomposition; Microelectronics; Prototypes; Signal processing algorithms; Throughput; Ultra large scale integration;

fLanguage

English

Journal_Title

Computer

Publisher

ieee

ISSN

0018-9162

Type

jour

DOI

10.1109/2.129054

Filename

129054