Designing synchronous circuits with partial asynchronous operation using clocked flip-flops with d.c. inputs

A practical design technique is developed that takes advantage of four inputs, J, K, S and R, often available on flip-flops to design circuits involving both synchronous and asynchronous behaviour. A compact state-table representation is described, along with the requirements for state reduction, assignment and circuit realisation. The technique can produce a saving in logic complexity over completely asynchronous designs.