Analytical Models for the Performance of von Neumann Multiplexing

As conventional silicon CMOS technology continues to shrink, logic circuits are increasingly subject to errors induced by electrical noise. In addition, device reliability will become a problem, and circuits will be subject to permanent faults. Rather than requiring the circuit to be defect-free, fault-tolerance techniques can be incorporated to allow the continued operation of these devices in the presence of defects. We present an improved model for the reliability of nand multiplexing, a fault-tolerance technique typically requiring large levels of redundancy. It extends previous models to account for dependence between the inputs and derives the distribution of the outputs of each stage when subject to errors. The Markov chain approach used in earlier models is shown to be correct in modeling the effect of multiple stages. Our new model produces more accurate results for moderate levels of redundancy. An example shows the required hardware redundancy is reduced by 50% versus the previous binomial model. In addition, three new types of errors are modeled: the output stuck-at-one, output stuck-at-zero, and input stuck-at-zero faults