Title :
Temporal Partitioning Data Flow Graphs for Dynamically Reconfigurable Computing
Author :
Jiang, Yung-Chuan ; Wang, Jhing-Fa
Author_Institution :
Nat. Cheng Kung Univ., Tainan
Abstract :
FPGA-based configurable computing machines are evolving rapidly in large signal processing applications due to flexibility and high performance. In this paper, given a reconfigurable processing unit (RPU) with a logic capacity of ARPU and a computational task represented by a data flow graph G = (V, E, W), we propose a network flow-based multiway task partitioning algorithm to minimize communication costs for temporal partitioning. The proposed algorithm obtains an optimal solution with minimum interconnection under area constraints. The optimal solution is a cut set. In our approach, two techniques are applied. In the initial partition, any feasible min-cut is produced by the proposed network flow-based algorithm, so a set of feasible min-cuts is obtained. From the feasible solutions, the scheduling technique selects an optimal global solution.
Keywords :
data flow graphs; field programmable gate arrays; reconfigurable architectures; scheduling; set theory; FPGA-based configurable computing machines; cut set; data flow graph; dynamically reconfigurable computing; field programmable gate array; network flow-based multiway task partitioning algorithm; optimal global solution; scheduling; signal processing application; temporal partitioning; Application software; Application specific integrated circuits; Computer architecture; Data flow computing; Field programmable gate arrays; Flow graphs; Hardware; Partitioning algorithms; Reconfigurable logic; Signal processing algorithms; Field-programmable gate array (FPGA); reconfigurable computing (RC); temporal partitioning;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2007.909806