DocumentCode :
966739
Title :
High-performance and low-power conditional discharge flip-flop
Author :
Zhao, Peiyi ; Darwish, Tarek K. ; Bayoumi, Magdy A.
Author_Institution :
Center for Adv. Comput. Studies, Univ. of Louisiana, Lafayette, LA, USA
Volume :
12
Issue :
5
fYear :
2004
fDate :
5/1/2004 12:00:00 AM
Firstpage :
477
Lastpage :
484
Abstract :
In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining the negative setup time and small D-to-Q delay characteristics. With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.
Keywords :
CMOS logic circuits; VLSI; delay circuits; flip-flops; integrated logic circuits; CMOS technology; D-to-Q delay characteristics; VLSI; conditional capture technologies; conditional discharge technology; data-switching activity; glitches; low-power conditional discharge flip-flop; pulsed flip-flops; redundant internal switching activities; Clocks; Delay effects; Flip-flops; Master-slave; Power dissipation; Power system interconnection; Pulse amplifiers; Pulse generation; Timing; Very large scale integration;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2004.826192
Filename :
1291426
Link To Document :
بازگشت