DocumentCode
966781
Title
Solder Fatigue Problems in Power Packages
Author
Burgess, James F. ; Carlson, Richard O. ; Glascock, Homer H., II ; Neugebauer, Constantine A. ; Webster, Harold F.
Author_Institution
General Electric Company, Schenectady, NY
Volume
7
Issue
4
fYear
1984
fDate
12/1/1984 12:00:00 AM
Firstpage
405
Lastpage
410
Abstract
The fatigue of solder connections in power packaging has been investigated. Power devices use large bond areas which lead to fatigue life problems. Three different types of structures consisting of silicon diodes attached to copper heatsinks have been thermally cycled and the integrity of the bonds compared. The thermal resistance from the silicon diode to its heatsink has been used to measure bond quality. Use of n BeO strain buffer between the silicon chip and the copper heatsink (Type II) improved the solder cycle life. Further addition of a layer of structured copper between the BeO and the copper sink (Type III resulted in marked additional improvement in cycle life. Fatigue failure was indicated by a rapid rise in the thermal resistance that suggested a crack or tear in one of the bonds between the silicon and the heat sink. This model has been confirmed by an ultrasonic microscope scan. Solder fatigue life was also extended by the use of hard solders, compressive forces, and hermeticity.
Keywords
Semiconductor device bonding; Semiconductor device packaging; Semiconductor device reliability; Soldering; Bonding; Copper; Diodes; Electrical resistance measurement; Fatigue; Heat sinks; Lead; Packaging; Silicon; Thermal resistance;
fLanguage
English
Journal_Title
Components, Hybrids, and Manufacturing Technology, IEEE Transactions on
Publisher
ieee
ISSN
0148-6411
Type
jour
DOI
10.1109/TCHMT.1984.1136381
Filename
1136381
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