Title :
Small area parallel Chien search architectures for long BCH codes
Author :
Chen, Yanni ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
fDate :
5/1/2004 12:00:00 AM
Abstract :
To implement parallel BCH (Bose-Chaudhuri-Hochquenghem) decoders in an area-efficient manner, this paper presents a novel group matching scheme to reduce the Chien search hardware complexity by 60% for BCH(2047, 1926, 23) code as opposed to only 26% if directly applying the iterative matching algorithm. The proposed scheme exploits the substructure sharing within a finite field multiplier (FFM) and among groups of FFMs.
Keywords :
BCH codes; iterative methods; BCH codes; Bose-Chaud-huri-Hochquenghem codes; Chien search hardware complexity; finite field multiplier; group matching scheme; iterative matching algorithm; parallel Chien search architectures; Bit error rate; Circuits; Clocks; Error correction codes; Galois fields; Hardware; Iterative algorithms; Iterative decoding; Optical fiber communication; Throughput;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2004.826203
