CMOS multiple-valued logic design. I. Circuit implementation

Author

Jain, Atul K. ; Bolton, Ron J. ; Abd-El-Barr, Mostafa H.

Author_Institution

Dept. of Electr. Eng., Saskatchewan Univ., Saskatoon, Sask., Canada

Volume

40

Issue

8

fYear

1993

fDate

8/1/1993 12:00:00 AM

Firstpage

503

Lastpage

514

Abstract

A CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed. The set consists of literal, cycle, complement of literal, complement of cycle, min, and tsum operators. In all of the circuits, multiple-valued logic levels are represented in terms of current values. Binary voltage signals are generated inside the circuits using a threshold circuit element. These binary voltage signals are used to generate control signals for switches to realize appropriate current levels for the desired multiple-valued logic levels. Transient analysis simulations (using HSPICE) to verify the functionality of the designed circuits and the effect of variation in process parameters are also reported

Keywords

CMOS integrated circuits; SPICE; circuit CAD; integrated logic circuits; logic CAD; many-valued logics; CMOS multiple-valued logic; HSPICE; binary voltage signals; circuit implementation; complement of cycle operators; complement of literal operators; current levels; cycle operators; literal operators; logic design; min operators; process parameters; threshold circuit element; transient analysis simulations; tsum operators; Analytical models; CMOS logic circuits; Circuit simulation; Logic circuits; Logic design; Signal generators; Switches; Threshold voltage; Transient analysis; Voltage control;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.242320

Filename

242320