Title :
Design of a high-performance, low-noise charge preamplifier
Author :
Wurtz, L.T. ; Wheless, W.P., Jr.
Author_Institution :
Dept. of Electr. Eng., Alabama Univ., Tuscaloosa, AL, USA
fDate :
8/1/1993 12:00:00 AM
Abstract :
A high-performance, low-noise charge preamplifier integrated circuit is designed and tested for the Superconducting Super Collider. The amplifier is fabricated in a new dielectrically isolated (DI), radiation-hardened, very-high-frequency (VHF) BIFET IC process technology from Harris Corporation. This new process provides n-p-n, p-n-p, and p-channel JFET devices which are both radiation-hardened, tested to 3 Mrad of total gamma ray exposure and 3×1014/cm2 neutron dosage, and provides high-frequency performance. The new charge preamplifier provides improved performance with an output rise time of 65 ns, input inferred noise of 28.6 μV, or 3575 electrons, and power dissipation less than 33.7 mW. The circuit design is discussed with attention given to those design characteristics needed to specifically accommodate low noise with the new radiation-hardened process
Keywords :
BIMOS integrated circuits; gamma-ray effects; integrated circuit technology; neutron effects; preamplifiers; proton accelerators; radiation hardening (electronics); storage rings; synchrotrons; 28.6 muV; 3 Mrad; 33.7 mW; 65 ns; JFET devices; Superconducting Super Collider; VHF BIFET IC process technology; design characteristics; dielectrically isolated technology; input inferred noise; low-noise charge preamplifier; neutron dosage; output rise time; power dissipation; radiation-hardened technology; total gamma ray exposure; Circuit noise; Circuit testing; Dielectrics; Integrated circuit technology; Integrated circuit testing; Isolation technology; Preamplifiers; Superconducting device noise; Superconducting integrated circuits; VHF circuits;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
