An ALU-Based BIST Scheme for Word-Organized RAMs

Testing of word-organized memories has been performed in one of these three ways: (1) by repeatedly applying a test for bit-oriented memories using different data backgrounds (which depend on the used intraword fault model), (2) by applying special tests to target intraword faults in addition to applying tests for bit-organized memories, or (3) by applying march tests bit-by-bit to the memory words. The latter solution results in decreased hardware overhead. In this paper, a novel Built-in Self-Test (BIST) scheme is proposed to serially apply march tests bit-by-bit to word-organized RAMs, utilizing an ALU whose inputs are driven by a barrel shifter. Comparisons with schemes that have been proposed in the open literature for the same purpose reveal that the proposed scheme achieves the same fault coverage within the same or lower time and with lower area overhead. More precisely, an overhead of n + 3 gates is required for the application of the required patterns to the RAM inputs and the evaluation of the corresponding outputs, as opposed to the 8n or 11n gates required by schemes proposed previously.