• DocumentCode
    968525
  • Title

    A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models

  • Author

    Daniel, Luca ; Siong, Ong Chin ; Chay, Low Sok ; Lee, Kwok Hong ; White, Jacob

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Massachusetts Inst. of Technol., Cambridge, MA, USA
  • Volume
    23
  • Issue
    5
  • fYear
    2004
  • fDate
    5/1/2004 12:00:00 AM
  • Firstpage
    678
  • Lastpage
    693
  • Abstract
    In this paper, we describe an approach for generating accurate geometrically parameterized integrated circuit interconnect models that are efficient enough for use in interconnect synthesis. The model-generation approach presented is automatic, and is based on a multiparameter moment matching model-reduction algorithm. A moment-matching theorem proof for the algorithm is derived, as well as a complexity analysis for the model-order growth. The effectiveness of the technique is tested using a capacitance extraction example, where the plate spacing is considered as the geometric parameter, and a multiline bus example, where both wire spacing and wire width are considered as geometric parameters. Experimental results demonstrate that the generated models accurately predict capacitance values for the capacitor example, and both delay and cross-talk effects over a reasonably wide range of spacing and width variation for the multiline bus example.
  • Keywords
    integrated circuit interconnections; integrated circuit modelling; network topology; reduced order systems; capacitance extraction; complexity analysis; crosstalk; geometrically parameterized interconnect performance models; integrated circuit models; integrated circuits interconnections; interconnect synthesis; model-order growth; multiline bus; multiparameter moment-matching model-reduction technique; reduced-order systems; Algorithm design and analysis; Capacitance; Capacitors; Integrated circuit interconnections; Integrated circuit modeling; Integrated circuit synthesis; Predictive models; Solid modeling; Testing; Wire;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2004.826583
  • Filename
    1291580