DocumentCode :
968556
Title :
Full-chip, three-dimensional shapes-based RLC extraction
Author :
Sitaram, Dipak ; Zheng, Yu ; Shepard, Kenneth L.
Author_Institution :
Cadence Design Syst., New Providence, NJ, USA
Volume :
23
Issue :
5
fYear :
2004
fDate :
5/1/2004 12:00:00 AM
Firstpage :
711
Lastpage :
727
Abstract :
In this paper, we report the development of a full-chip, three-dimensional, shapes-based, resistence-inductance-capacitance extraction tool, which was developed as part of a university-industry collaboration. The technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible "nominal" values in the absence of mutual coupling. Mutual inductances are extracted for accurate crosstalk analysis. The tool exploits high-capacity scan-band techniques and disk caching. Accuracy is validated by comparison with full-wave finite-element field solvers.
Keywords :
capacitance; crosstalk; finite element analysis; inductance; integrated circuit interconnections; integrated circuit modelling; RLC; crosstalk analysis; disk caching; finite-element field solvers; frequency-independent inductance; full-chip; full-wave solvers; interconnect modeling; mutual coupling; mutual inductances; parasitic extraction; resistance network; resistence-inductance-capacitance; return-limited inductances; scan-band techniques; self-inductances; Capacitance; Coupling circuits; Crosstalk; Engines; Finite element methods; Frequency; Inductance; Integral equations; Integrated circuit interconnections; RLC circuits;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2004.826545
Filename :
1291583
Link To Document :
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