Title :
Debug architecture for the En-II system chip
Author :
Vermeulen, B. ; Bakker, S.
Author_Institution :
Corp. I&T/Res., Eindhoven
Abstract :
A comprehensive system debug methodology is presented, which combines the state-of-the-art support for software, functional hardware and process technology debug. The application of this methodology to the 65-nm CMOS En-II SoC is described, containing among others a high-performance ARM CPU and a TriMedia VLIW DSP. The debug requirements and implementation choices made are explained in detail.
Keywords :
CMOS integrated circuits; electronic engineering computing; logic design; parallel architectures; program debugging; system-on-chip; CMOS En-II SoC; En-ll system chip; TriMedia VLIW DSP; debug architecture; high-performance ARM CPU; size 65 nm; system debug;
Journal_Title :
Computers & Digital Techniques, IET
DOI :
10.1049/iet-cdt:20060217
