Title :
CPC (cyclic pipeline computer)-an architecture suited for Josephson and pipelined-memory machines
Author :
Shimizu, Kentaro ; Goto, Eiichi ; Ichikawa, Shuichi
Author_Institution :
Dept. of Inf. Sci., Tokyo Univ., Japan
fDate :
6/1/1989 12:00:00 AM
Abstract :
Describes a novel computer architecture, called a cyclic pipeline computer (CPC), which is especially suited for Josephson technologies. Since each Josephson logic device acts as a latch, it is possible to use high-pitch and shallow logic pipelining without any increase in delay time and cost. Hence, both the processor and the main memory can be built from the Josephson devices and can be pipelined with the same pipeline pitch time. The CPC supports multiple instruction/multiple data stream (MIMD) by time-sharing the processor and the main memory among multiple instruction streams. In addition, it employs advanced control to speed up the computation for each instruction stream
Keywords :
parallel architectures; CPC; Josephson technologies; MIMD; architecture; cyclic pipeline computer; multiple instruction streams; pipelined-memory machines; time-sharing; Computer aided instruction; Computer architecture; Costs; Delay effects; Josephson junctions; Logic devices; Pipeline processing; Registers; Silicon; Synchronization;
Journal_Title :
Computers, IEEE Transactions on