Testing SoC interconnects for signal integrity using extended JTAG architecture

Author

Tehranipour, Mohammad H. ; Ahmed, Nisar ; Nourani, Mehrdad

Author_Institution

Center for Integrated Circuits & Syst., Univ. of Texas, Richardson, TX, USA

Volume

23

Issue

5

fYear

2004

fDate

5/1/2004 12:00:00 AM

Firstpage

800

Lastpage

811

Abstract

As technology shrinks and working frequency reaches the multigigahertz range, designing and testing interconnects are no longer trivial issues. In this paper, we propose an enhanced boundary-scan architecture to test high-speed interconnects for signal integrity. This architecture includes: 1) a modified driving cell that generates patterns according to multiple transitions fault model and 2) an observation cell that monitors signal integrity violations. To fully comply with the conventional Joint Test Action Group Standard, two new instructions are used to control cells and scan activities in the integrity test mode.

Keywords

boundary scan testing; integrated circuit design; integrated circuit interconnections; integrated circuit testing; system-on-chip; Joint Test Action Group Standard; SoC; boundary-scan test; driving cell; extended JTAG architecture; integrity loss; interconnects design; interconnects testing; multiple transitions fault model; observation cell; signal integrity; system-on-chip; Circuit noise; Circuit testing; Crosstalk; Delay; Frequency; Inductance; Integrated circuit interconnections; Mutual coupling; Parasitic capacitance; Signal generators;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2004.826540

Filename

1291589