Title :
Multiplier/shifter design tradeoffs in a 32-bit microprocessor
Author :
Milutinovic ; Bettinger, Mark ; Helbig, Walter
Author_Institution :
Sch. of Electr. Eng., Purdue Univ., West Lafayette, IN, USA
fDate :
6/1/1989 12:00:00 AM
Abstract :
The authors concentrate on design tradeoffs between the bit-serial multiplier and the full barrel shifter combined with a large register file. They analyze and compare three alternatives for a given set of technology related parameters and a given set of higher level language (HLL) benchmarks. Although their basic concern is the design of a 32-bit GaAs microprocessor on a single chip, the implications of the results are more general
Keywords :
logic design; microprocessor chips; 32 bits; GaAs microprocessor; bit-serial multiplier; design tradeoffs; full barrel shifter; large register file; microprocessors; single chip; CMOS technology; Delay; Gallium arsenide; Laboratories; Microprocessors; Packaging; Performance analysis; Registers; Silicon; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
